HDI Design Rules: Minimum Via Sizes & Spacing

Small holes lie.

I have seen HDI layouts that looked beautiful in CAD and then turned ugly inside the factory quotation process, not because the circuit idea was bad, not because the engineer was careless, but because the via structure asked the manufacturer to do three risky things at once: drill smaller, plate deeper, and keep spacing tight under a thermal profile that would punish every weak interface.

So what failed first?

Usually not the line width. Usually not the solder mask. Usually not the finish. The silent killer is the via rule set: minimum microvia size, pad diameter, capture land, via-to-via spacing, via-to-trace spacing, stacked-via decision, and whether the designer treated IPC limits as production comfort or as a cliff edge. IPC-related definitions commonly describe a microvia as a blind structure with a maximum 1:1 aspect ratio and a total depth not exceeding 0.25 mm, which is already a warning that “small” is not the same as “free.”

HDI PCB Design Rules Are Not Decoration

HDI PCB design rules are the manufacturing boundary between a dense layout and a board that can survive drilling, plating, lamination, reflow, inspection, and field use. A layout rule is not just a number in Altium, Cadence, KiCad, or Mentor. It is a contract with chemistry, laser energy, copper distribution, resin movement, and yield.

Hard truth: many HDI problems begin before the PCB supplier sees the Gerber.

The design team often starts from the BGA pitch. Then the layout gets squeezed. Then the via diameter is reduced. Then the pad shrinks. Then spacing gets cut. At the end, someone sends a ZIP file and expects the factory to “check DFM.” That is backwards. For complex HDI, the stack-up and via structure should be discussed before fanout, especially when the project uses 0.4 mm BGA, 0.35 mm BGA, high-speed signals, rigid-flex sections, or RF material.

If the design is still in the concept stage, a multilayer PCB manufacturing with Gerber DFM service is not paperwork. It is insurance. The earlier the via rules are checked, the fewer heroic compromises happen later.

The Minimum Via Size Is Not One Universal Number

Here is my unpopular opinion: asking “What is the minimum via size?” without stack-up information is like asking “How fast can a truck turn?” without road width, cargo weight, tire type, and weather.

Yes, typical HDI microvias often sit around 75–150 µm laser-drilled diameter, and many production-friendly HDI designs use 100 µm microvias because the process window is less fragile. But the real answer depends on dielectric thickness, copper foil thickness, plating requirement, whether the via is filled, whether it is stacked, and what reliability class the product must meet.

A 75 µm microvia through a thin dielectric may be reasonable. A 75 µm microvia through a thicker dielectric can become a plating gamble. A 100 µm microvia with clean aspect ratio may be boring. Boring is good.

I like boring.

For many commercial HDI projects, I would rather see a stable 100 µm microvia with enough capture pad than an aggressive 50–60 µm microvia that saves routing space but creates yield pain, price inflation, and longer engineering discussion. If the board is for AI hardware, medical equipment, automotive control, aerospace, telecom infrastructure, or a long-life industrial controller, minimum via size should be treated as a reliability variable, not just a routing shortcut.

Why Aspect Ratio Matters More Than the Hole Diameter

A via is not a dot. It is a plated vertical structure.

Aspect ratio compares via depth to via diameter. For microvias, keeping the aspect ratio conservative helps copper plating reach the bottom of the via and bond properly to the target pad. When designers force a small microvia through a dielectric that is too thick, the bottom interface becomes the weak point. That is where cracks, opens, and intermittent failures love to hide.

IPC has warned the industry about high-performance PCB microvia reliability, especially weak interfaces between microvia target pads and electrolytic copper fill in stacked structures. That warning was not marketing drama; it reflected real OEM concern about latent field failures that may not appear during basic electrical test.

That is the ugly part. A bad microvia can pass today and fail later.

In practical language, the safer starting point is simple: keep laser microvias shallow, use a reasonable diameter, avoid unnecessary multi-level stacking, and confirm whether the fabricator prefers 0.75:1, 0.8:1, or another internal limit for the build. The official limit may say one thing. The factory’s stable yield may say something stricter.

Minimum Microvia Size: Practical Starting Points

For standard HDI PCB layout guidelines, these numbers are not magic rules. They are negotiation starters.

HDI Feature	Safer Starting Point	Aggressive Range	Main Risk If Pushed Too Far
Laser microvia diameter	100 µm	75–80 µm	Poor plating at via bottom
Microvia finished depth	≤100 µm preferred	Up to 250 µm by definition limit	Higher aspect ratio stress
Microvia pad diameter	250–300 µm	200–225 µm	Weak annular ring / registration loss
Via-to-trace spacing	75–100 µm	50–60 µm	Etching yield loss / shorts
Via-to-via spacing	100–150 µm	75 µm	CAF risk / registration pressure
BGA escape pitch	0.5 mm easier	0.4 mm and below	More lamination and microvia cost
Stacked microvia levels	1–2 levels preferred	3+ levels	Interface fatigue and hidden opens
Staggered microvias	Preferred for reliability	Less dense than stacked	More routing space needed

Do not copy this table blindly.

Use it to start the conversation. The final HDI PCB via size and spacing should be locked with the PCB manufacturer after stack-up review, copper weight review, material selection, and impedance requirement review. If the PCB also has RF paths, for example, the via design has to work with material loss, reference plane behavior, and controlled impedance, not only routing density. That is why high-frequency designs should be reviewed together with a high-frequency Rogers RF PCB prototype process, not treated like ordinary FR-4 routing.

HDI PCB Spacing Rules: Where Designers Cheat Too Much

Spacing feels flexible in CAD. It is not flexible in copper.

HDI PCB spacing rules usually cover trace-to-trace, via-to-via, via-to-pad, via-to-trace, copper-to-edge, solder mask dam, and clearance around buried or blind via structures. The problem is that many layouts use one global clearance rule when the board really needs several local rules.

A 100 µm clearance may work in one area. Under a 0.4 mm BGA, the same number may be too loose to route. Near high voltage, it may be too tight. Around a via-in-pad feature, it may not address solder wicking or planarization. Around rigid-flex transition zones, it may ignore bend stress entirely.

This is why I dislike “minimum everything” design.

Minimum line. Minimum space. Minimum via. Minimum annular ring. Minimum solder mask dam. Minimum copper clearance. Minimum quote time. Then everyone acts surprised when the price doubles.

For mixed technology boards, especially when HDI features meet flexible sections, spacing rules must also consider mechanical behavior. If the design includes bend areas, connectors, or compact cable-like sections, check the HDI part together with flexible FPC prototype cable design instead of assuming rigid PCB spacing habits will transfer safely.

Blind Via and Buried Via Spacing: The Stack-Up Decides the Bill

Blind via and buried via spacing is not only a geometry issue. It decides lamination sequence, drilling method, plating flow, inspection difficulty, and cost.

A blind via connects an outer layer to an inner layer. A buried via connects internal layers and is hidden after lamination. A microvia is often a laser-drilled blind via, but not every blind via is automatically a microvia. That distinction matters because the manufacturing route changes.

Here is the practical cost logic:

If you use one laser microvia from L1 to L2, the build is manageable.

If you add L1-L2 and L2-L3 stacked microvias, the manufacturer may need filling, planarization, and another build-up cycle.

If you add buried vias from L3-L6 plus stacked microvias above them, the process becomes more expensive and more sensitive to alignment.

If you stack microvias on top of buried mechanical vias, the structure may be dense, but the reliability conversation gets serious.

The IPC warning on microvia reliability is one reason I tell customers not to chase stacked structures unless they truly need them. For 0.4 mm BGA escape, maybe yes. For a design that could be solved with staggered vias and one more routing channel, maybe no.

And if the product is high-temperature or has large copper areas, material stability becomes part of the via decision. In that case, a high-Tg mainboard PCB assembly with large copper areas is more relevant than a generic low-cost HDI quote.

The Dirty Secret: Smaller Vias Can Increase PCB Size Risk

This sounds strange. Smaller vias should save space, right?

Sometimes. But aggressive via rules can force process constraints that create other layout compromises: larger pads for reliability, extra spacing for yield, additional lamination cycles, changed copper balance, more test coupons, or rework of the fanout plan. The final PCB may not shrink as much as expected. The cost definitely may not shrink.

In November 2024, IPC reported North American PCB bookings up 29.1% year over year and a book-to-bill ratio of 1.15, which means demand pressure was already visible in order flow, not just in supplier talk. When factories are busy, designs with unstable HDI rules do not get cheaper; they get questioned harder.

So I would not design HDI around the smallest published capability. I would design around the smallest repeatable capability.

There is a difference.

Via-in-Pad: Useful, Expensive, and Often Misused

Via-in-pad is useful when escaping fine-pitch BGA packages, shortening signal paths, improving power delivery, or reducing stubs. It can be the right choice for 0.4 mm pitch BGA, dense IoT modules, RF modules, high-speed processors, and compact medical electronics.

But via-in-pad is not just “put the via in the pad.” It usually requires filling, plating over, planarization, and strict surface flatness control. If the via is not properly filled and capped, solder can wick into the hole, causing weak joints, voids, or uneven assembly.

For dense IoT and high-speed compact electronics, via-in-pad may be worth it. That is where a high-frequency HDI IoT turnkey PCB service fits the design discussion better than a standard two-layer PCB supplier conversation.

But if your BGA pitch does not require via-in-pad, do not use it just because it looks advanced. Advanced is not the goal. Passing production is the goal.

Stacked vs Staggered Microvias: My Strong Opinion

Use staggered microvias when you can.

Stacked microvias are clean, compact, and powerful. They also concentrate stress vertically. Every stacked interface needs excellent fill, plating, lamination, and registration. If the board goes through multiple reflow cycles, thermal cycling, or long field use, that vertical column becomes a reliability question.

Staggered microvias spread the structure sideways. They consume more routing area, but they usually reduce interface stress. In many industrial, medical, automotive, and aerospace-like designs, I would take slightly larger routing space over a fragile vertical stack.

Is stacked always wrong? No.

For fine-pitch BGA escape, stacked vias may be the only clean route. For very compact HDI modules, they can be necessary. But the design should state exactly how many stacked levels are used, whether they are copper-filled, whether they sit over buried mechanical vias, and what test coupon or reliability requirement is expected.

A vague note like “use HDI vias as needed” is not a design rule. It is a future argument.

How to Set HDI Design Rules Before Layout

I would set HDI PCB design rules in this order:

First, define the component pitch. A 0.5 mm BGA and a 0.35 mm BGA are different worlds.

Second, define the stack-up. Decide whether the board is 1+N+1, 2+N+2, sequential lamination, rigid-flex, or a mixed RF structure.

Third, set the via family. Do not mix every possible via type unless there is a reason.

Fourth, define the minimum microvia size and pad diameter.

Fifth, define via spacing by zone: BGA fanout zone, high-speed zone, power zone, flex transition zone, and general routing zone.

Sixth, confirm copper weight. Heavy copper and tiny HDI spacing are not friendly neighbors.

Seventh, send the rules to the manufacturer before routing becomes emotionally expensive.

That last phrase matters. Engineers get attached to layouts. Once the routing is complete, changing via rules feels like losing work. But a PCB factory does not care how long the routing took. The copper either works or it does not.

Common HDI Rule Mistakes I See Too Often

One mistake is treating IPC as the only requirement. IPC gives a framework, but each PCB factory has process windows, equipment limits, material preferences, and yield history.

Another mistake is using the same annular ring for laser microvias and mechanical vias. They do not behave the same.

A third mistake is ignoring resin thickness. Designers ask for a 75 µm microvia but forget that the dielectric thickness makes the aspect ratio uncomfortable.

A fourth mistake is stacking too many microvias without asking how they will be filled and planarized.

A fifth mistake is using blind via and buried via spacing rules without considering test access and inspection.

A sixth mistake is forcing high-speed signals through via structures that were chosen for density, not signal quality.

That one hurts.

In RF, high-speed digital, and impedance-sensitive designs, via geometry changes return current, stub behavior, capacitance, and insertion loss. A small via may solve fanout while quietly damaging signal integrity. For this reason, HDI design rules should be reviewed with stack-up, impedance, and material selection together, especially when Rogers, PTFE, low-Dk, or hybrid material systems are involved.

FAQ

What is the minimum via size for HDI PCB?

The minimum via size for an HDI PCB is the smallest laser-drilled or mechanically drilled hole a fabricator can plate reliably while meeting the board’s dielectric thickness, copper thickness, aspect ratio, annular ring, and reliability class, so it must be confirmed against the actual stack-up before layout. In practical HDI production, 100 µm microvias are often a safer starting point than chasing the smallest advertised number.

What is the typical minimum microvia size?

The typical minimum microvia size is often around 75–100 µm for laser-drilled HDI structures, but the stable production value depends on dielectric thickness, copper weight, via fill requirement, plating process, capture pad size, and whether the via is single-level, stacked, or staggered. I normally treat 100 µm as a practical baseline for manufacturability discussions.

What are HDI PCB spacing rules?

HDI PCB spacing rules define the minimum allowed clearance between traces, vias, pads, copper features, solder mask openings, planes, and board edges so the PCB can be etched, drilled, plated, laminated, inspected, and assembled without shorts, weak copper, registration failure, or yield loss. These rules should change by design zone, not stay global.

Are stacked microvias reliable?

Stacked microvias are reliable only when the structure, material, fill process, plating quality, lamination sequence, and thermal stress profile are controlled tightly enough to protect every copper-to-copper interface through assembly and field use. For many designs, staggered microvias give a safer reliability margin, even though they need more routing room.

What is the difference between blind vias and buried vias?

A blind via connects an outer PCB layer to one or more internal layers, while a buried via connects only internal layers and is hidden after lamination, so both structures increase routing density but also add process steps, cost, registration demands, and inspection difficulty. HDI designs often combine blind microvias with buried vias in sequential build-ups.

How should engineers choose HDI PCB via size and spacing?

Engineers should choose HDI PCB via size and spacing by starting from component pitch, stack-up, dielectric thickness, copper weight, reliability class, impedance needs, assembly profile, and the PCB manufacturer’s stable process window rather than copying generic minimum values from a capability chart. The best rule is the one the factory can repeat, not just quote.

Conclusion

HDI design rewards discipline.

A dense layout can look impressive on a monitor, but the real test happens in drilling, plating, lamination, reflow, and field life. Minimum via size and spacing are not just layout settings. They are cost controls, reliability controls, and schedule controls.

If your project uses fine-pitch BGA, blind vias, buried vias, via-in-pad, stacked microvias, rigid-flex sections, high-Tg material, or RF material, send the stack-up and Gerber data for DFM review before locking the layout. MCHDIPCB can review HDI PCB design rules, check via feasibility, and help adjust the design toward a buildable production route without wasting weeks on avoidable revisions.